An Integrated Circuit (IC) comprises millions of individual transistor or logical circuits, e.g., memory cells.
A die or chip is the smallest manufactured unit form of integrated circuits. They are fabricated in a large array on a single substrate called wafer. The wafer is then cut into individual dice or chips. Chips can be encapsulated into packages, most often one chip per package and sometimes several of them together. Packages are provided with leads for mounting on a Printed Circuit (PC) board to create an electronic module, e.g., a memory module. Sometimes the package state is bypassed and chips are mounted directly on a PC board, e.g., the so-called Chip-On-Board (COB) assembly. Validity tests can be performed on single chips at the wafer level, on individual packages, or on entire modules. Each wafer, package or module may contain manufacturing flaws that invalidate portions of, or whole chips.
The impact of the manufacturing flaws are most often limited so that substantial portions of defective chips remain unaffected. It is common practice to use an excess number of partially good chips, package or modules to assemble a complete memory unit that normally would require a lesser number of fully operating ones. For example, a 1M×9 Single In-line Memory Module (SIMM) could be made with three partially good 1M×3 Dynamic Random Access Memory (DRAM) chip or package sections in lieu of two flawless 1M×4 chips or packages and one 1M×1 flawless one for the parity bit. The identification, isolation and combination of operating segments of partially defective chips, packages or modules often require complex procedures and bulky circuits due to the great number of possible combinations whether or not one tries to combine chips or packages on a single module, or wire together several modules. The new higher density memories have compounded the complexity of such combinations.
IC manufacturers use various types of self-correcting techniques in order to improve the quality of their chips. For example, a series of redundant or spare cells are built into a die. At the wafer level, the die is tested. The defective cells are isolated and some of the spare cells are wired in their place such as by blowing fuse sections prebuilt on the chip. In spite of these highly effective correction techniques, defects are still detected in chips before and after they are encapsulated into packages or assembled on COB modules. The packaging and assembly processes sometimes cause some chips failure. The high cost of high-density chips make the use of less-than-perfect ones an economic necessity. Yet, the prior art does not offer a systematic and efficient approach to the combination of less-than-perfect chips or packages with or without “perfect” ones in order to create economically advantageous memory modules. The instant invention results from a search for quick, versatile and economical processes to assemble memory modules out of less-than-perfect chips.